URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Rev 68

Rev	Log message	Author	Age	Path
62	Removed the pipe logic from the non-pipelined version, and made the NOOP a specific ALU instruction so that the PC is always properly updated.	dgisselq	3091d 05h	/xulalx25soc/trunk/rtl/cpu/idecode.v
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	3139d 06h	/xulalx25soc/trunk/rtl/cpu/idecode.v
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	3149d 04h	/xulalx25soc/trunk/rtl/cpu/idecode.v
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	3158d 07h	/xulalx25soc/trunk/rtl/cpu/idecode.v
26	Some bug fixes, and the long jump early branching integration.	dgisselq	3182d 08h	/xulalx25soc/trunk/rtl/cpu/idecode.v
23	This fixes a bug in the early branching system, and clarifies that early branch instructions will not affect the flags. It's a basic bug fix update.	dgisselq	3190d 18h	/xulalx25soc/trunk/rtl/cpu/idecode.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3243d 17h	/xulalx25soc/trunk/rtl/cpu/idecode.v