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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Rev 86

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Rev Log message Author Age Path
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.		 dgisselq 2993d 18h /xulalx25soc/trunk/rtl/cpu/idecode.v
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 2999d 15h /xulalx25soc/trunk/rtl/cpu/idecode.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3047d 16h /xulalx25soc/trunk/rtl/cpu/idecode.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 3057d 14h /xulalx25soc/trunk/rtl/cpu/idecode.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 3066d 17h /xulalx25soc/trunk/rtl/cpu/idecode.v
26 Some bug fixes, and the long jump early branching integration. dgisselq 3090d 18h /xulalx25soc/trunk/rtl/cpu/idecode.v
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.		 dgisselq 3099d 04h /xulalx25soc/trunk/rtl/cpu/idecode.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3152d 03h /xulalx25soc/trunk/rtl/cpu/idecode.v

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