URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 77

Rev	Log message	Author	Age	Path
73	Simplified logic.	dgisselq	3046d 07h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	3094d 08h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	3104d 06h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	3113d 09h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
46	This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v from working when long pipelined reads were interrupted by the necessity of a pair of refresh cycles.	dgisselq	3124d 11h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
26	Some bug fixes, and the long jump early branching integration.	dgisselq	3137d 10h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3198d 19h	/xulalx25soc/trunk/rtl/cpu/zipcpu.v