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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 89

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89 Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done.		 dgisselq 2908d 15h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
73 Simplified logic. dgisselq 2914d 11h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2962d 12h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2972d 11h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2981d 13h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2992d 15h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
26 Some bug fixes, and the long jump early branching integration. dgisselq 3005d 15h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3067d 00h /xulalx25soc/trunk/rtl/cpu/zipcpu.v

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