URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipsystem.v] - Rev 104

Rev	Log message	Author	Age	Path
98	Updated copyright notices for the new year, to reflect that changes have been made in 2016.	dgisselq	3079d 01h	/xulalx25soc/trunk/rtl/cpu/zipsystem.v
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	3108d 01h	/xulalx25soc/trunk/rtl/cpu/zipsystem.v
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	3156d 02h	/xulalx25soc/trunk/rtl/cpu/zipsystem.v
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	3166d 00h	/xulalx25soc/trunk/rtl/cpu/zipsystem.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3260d 14h	/xulalx25soc/trunk/rtl/cpu/zipsystem.v