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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipsystem.v] - Rev 118

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118 Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore.		 dgisselq 2935d 03h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
117 Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location.		 dgisselq 2959d 18h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 3052d 20h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
98 Updated copyright notices for the new year, to reflect that changes have been
made in 2016.		 dgisselq 3061d 14h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
68 Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation.		 dgisselq 3090d 15h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3138d 16h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 3148d 14h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3243d 03h /xulalx25soc/trunk/rtl/cpu/zipsystem.v

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