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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipsystem.v] - Rev 67

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52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.
dgisselq 3142d 15h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.
dgisselq 3152d 14h /xulalx25soc/trunk/rtl/cpu/zipsystem.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3247d 03h /xulalx25soc/trunk/rtl/cpu/zipsystem.v

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