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[/] [xulalx25soc/] [trunk/] [rtl/] [sdspi.v] - Rev 113

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113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.
dgisselq 3053d 05h /xulalx25soc/trunk/rtl/sdspi.v
100 Includes updates so this can run at higher clocks speeds within an FPGA. dgisselq 3061d 23h /xulalx25soc/trunk/rtl/sdspi.v
90 Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional.
dgisselq 3085d 03h /xulalx25soc/trunk/rtl/sdspi.v
85 First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.)
dgisselq 3089d 01h /xulalx25soc/trunk/rtl/sdspi.v

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