URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [toplevel.v] - Rev 114

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	3056d 20h	/xulalx25soc/trunk/rtl/toplevel.v
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	3094d 15h	/xulalx25soc/trunk/rtl/toplevel.v
48	Cleaned up the documentation a touch. It no longer reads like the bugs I used to debug are still being debugged ...	dgisselq	3172d 18h	/xulalx25soc/trunk/rtl/toplevel.v
18	Got the bitfile back up to speed at 80 MHz.	dgisselq	3250d 17h	/xulalx25soc/trunk/rtl/toplevel.v
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3252d 16h	/xulalx25soc/trunk/rtl/toplevel.v
2	A very first, albeit incomplete, build.	dgisselq	3255d 13h	/xulalx25soc/trunk/rtl/toplevel.v