URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [wbucompress.v] - Rev 114

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	3053d 03h	/xulalx25soc/trunk/rtl/wbucompress.v
109	This continues the updates to the wishbone-uart conversion. It fixes several bugs within wbuexec, and pipelines the compression scheme. Further, the read codeword was adjusted so that a read of 8 can be requested with six-bits, rather than requiring 12. Likewise, the dependence upon the read of 8 on incrementing the address pointer has been removed. All told, the design builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing flash seems to be one of the most comprehensive tests ...)	dgisselq	3061d 11h	/xulalx25soc/trunk/rtl/wbucompress.v
43	Commentary changes only, no substance.	dgisselq	3172d 21h	/xulalx25soc/trunk/rtl/wbucompress.v
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3248d 23h	/xulalx25soc/trunk/rtl/wbucompress.v
2	A very first, albeit incomplete, build.	dgisselq	3251d 20h	/xulalx25soc/trunk/rtl/wbucompress.v