URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [wbufifo.v] - Rev 113

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	3052d 23h	/xulalx25soc/trunk/rtl/wbufifo.v
102	Updated documentation. The documentation for these now also reflects that these were drawn from an FPGA Library project, that is shared among many FPGA builds.	dgisselq	3061d 17h	/xulalx25soc/trunk/rtl/wbufifo.v
59	Simplified logic.	dgisselq	3090d 19h	/xulalx25soc/trunk/rtl/wbufifo.v
2	A very first, albeit incomplete, build.	dgisselq	3251d 16h	/xulalx25soc/trunk/rtl/wbufifo.v