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[/] [xulalx25soc/] [trunk/] [rtl/] [wbusixchar.v] - Rev 116

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102 Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds.
dgisselq 3065d 20h /xulalx25soc/trunk/rtl/wbusixchar.v
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.
dgisselq 3252d 22h /xulalx25soc/trunk/rtl/wbusixchar.v
2 A very first, albeit incomplete, build. dgisselq 3255d 19h /xulalx25soc/trunk/rtl/wbusixchar.v

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