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[/] [xulalx25soc/] [trunk/] [sw/] [regdefs.cpp] - Rev 103

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103 Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.)		 dgisselq 3061d 21h /xulalx25soc/trunk/sw/regdefs.cpp
77 Adds register names and values for the SD card interface. dgisselq 3090d 21h /xulalx25soc/trunk/sw/regdefs.cpp
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3181d 00h /xulalx25soc/trunk/sw/regdefs.cpp
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3247d 01h /xulalx25soc/trunk/sw/regdefs.cpp
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3251d 19h /xulalx25soc/trunk/sw/regdefs.cpp

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