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[/] [xulalx25soc/] [trunk/] [sw/] [zipdbg.cpp] - Rev 111

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110 Fixed a problem whereby block RAM would be declared as a bus error on the
stack, even if the data was valid.		 dgisselq 3061d 06h /xulalx25soc/trunk/sw/zipdbg.cpp
92 Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger.		 dgisselq 3085d 01h /xulalx25soc/trunk/sw/zipdbg.cpp
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.		 dgisselq 3090d 21h /xulalx25soc/trunk/sw/zipdbg.cpp
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3181d 00h /xulalx25soc/trunk/sw/zipdbg.cpp
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3251d 09h /xulalx25soc/trunk/sw/zipdbg.cpp
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3251d 19h /xulalx25soc/trunk/sw/zipdbg.cpp

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