URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] [zipdbg.cpp] - Rev 82

Rev	Log message	Author	Age	Path
76	Now tries to avoid reading from the stack if the stack addresses are already known to be bad. That way, the debugger tries to preserve any bus error address already on the buserr device.	dgisselq	3084d 14h	/xulalx25soc/trunk/sw/zipdbg.cpp
31	A bug fix, although one that rearranges the bus. The first four I/O locations have been adjusted. The new locations are reflected in wishbone.html. In addition, the PWM and UART devices no longer create bus errors when accessed. Finally, this version uses a `define XULA25 to determine whether or not to build for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define would be to place it into your Xilinx configuration, should you wish to build for the LX25.	dgisselq	3174d 17h	/xulalx25soc/trunk/sw/zipdbg.cpp
7	Mostly minor changes. Fixed the legal copyright statement in the UART files, adjusted some comments, and made sure that the zipdbg program contained all the latest features from our Vault.	dgisselq	3245d 02h	/xulalx25soc/trunk/sw/zipdbg.cpp
5	Initial software version, in support of the project. At this point, they are provided with no guarantees that they work. (They did use to work--on an older build, but I haven't been able to verify that they work with this newer build yet.)	dgisselq	3245d 12h	/xulalx25soc/trunk/sw/zipdbg.cpp