URL https://opencores.org/ocsvn/yac/yac/trunk

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[/] [yac/] [trunk/] [rtl/] [vhdl/] [cordic_iterative_tb.vhd] - Rev 4

Rev	Log message	Author	Age	Path
4	Updated C and RTL model as well as the documentation	feddischson	3442d 23h	/yac/trunk/rtl/vhdl/cordic_iterative_tb.vhd
3	initial commit	feddischson	3442d 23h	/yac/trunk/rtl/vhdl/cordic_iterative_tb.vhd
2	First stable version: RTL model is verified with C-model via RTL simulations.	feddischson	3892d 10h	/yac/trunk/rtl/vhdl/cordic_iterative_tb.vhd