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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [digital_core/] [src/] [digital_core.sv] - Rev 23

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21 Simulation clean up and wishbone interconnect added dinesha 1250d 16h /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/digital_core.sv
20 digital core added into svn dinesha 1255d 07h /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/digital_core.sv

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