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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_regs.sv] - Rev 21

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21 Simulation clean up and wishbone interconnect added dinesha 1265d 06h /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv
18 spi master added dinesha 1270d 02h /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv

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