OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [Makefile] - Rev 63

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
58 Added a rudimentary profiling support to the simulator. dgisselq 3301d 20h /zipcpu/trunk/bench/cpp/Makefile
43 Minor edits to the C++ testbench. dgisselq 3321d 14h /zipcpu/trunk/bench/cpp/Makefile
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3324d 17h /zipcpu/trunk/bench/cpp/Makefile
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3333d 22h /zipcpu/trunk/bench/cpp/Makefile
27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.		 dgisselq 3363d 10h /zipcpu/trunk/bench/cpp/Makefile
2 An initial load. No promises of what works or not, but this is where the
project is at.		 dgisselq 3389d 14h /zipcpu/trunk/bench/cpp/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.