URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [Makefile] - Rev 33

Rev	Log message	Author	Age	Path
18	A couple of changes: Registers can now be changed via the debug interface. Also, in anticipation of being able to interrupt the break the processor, the CPU now exports an interrupt line to the external environment to tell when it has been halted. Thus, if it gets halted by a break instruction, the ZipSystem will interrupt whatever's in its environment so that the debugger can come and examine its state. Oh, and one other: because you can't examine the state of the CPU without halting it, I modified the debug control register to export the four useful flags: break-enable, interrupts enabled, and sleep (step comes for free in this implementation).	dgisselq	3395d 10h	/zipcpu/trunk/rtl/Makefile
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3415d 14h	/zipcpu/trunk/rtl/Makefile