URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Rev 18

Rev	Log message	Author	Age	Path
15	Updated the core CPUOPS module to make certain that the carry was properly set on right shifts. (Carry is then the last bit shifted out to the right, and has no relation to the high order bits of the word.) Also fixed a bug in the busdelay.v file that prevented our Quad SPI flash controller from working. (This bug fix has not yet been tested ...) Our test.S program, the closest thing we have to a regression test and found in the sw/zasm directory, still successfully passes in Verilator.	dgisselq	3373d 10h	/zipcpu/trunk/rtl/aux/busdelay.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3390d 00h	/zipcpu/trunk/rtl/aux/busdelay.v