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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Rev 182

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Rev	Log message	Author	Age	Path
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3244d 11h	/zipcpu/trunk/rtl/aux/busdelay.v
61	Simplified the bus delay logic. Depends upon the stall line being irrelevant outside of a bus cycle.	dgisselq	3305d 11h	/zipcpu/trunk/rtl/aux/busdelay.v
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3337d 14h	/zipcpu/trunk/rtl/aux/busdelay.v
34	Bunches of changes, although very little changed with the core itself. Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the core), so that the debugger can change the program counter. The debugger can now halt the CPU and then view, examine, and modify registers to include the program counter, although live changes to the CC register have not been tested. There was also a bug in the stall handling of the wishbone bus delay line. This has now been fixed. Moving outwards to the system, some parameters have been added to zipsystem to make it more configurable for whatever environment you might wish to place it within. Other minor clean ups have taken place, mostly to the internal documentation. Lots of changes, though, to the assembler. The big one is the implementation of #define macros, C style. Several buggy macros were in sys.i. These have been fixed. The Makefile has been adjusted so that the build of test.S, which depends upon sys.i, is now properly dependent upon sys.i for make purposes. Further, not only will zpp, the assembler preprocessor, handle #define macros, it will also recursive #defines. The assembler expression evaluator has also been updated to properly handle both operator precedence, as well as modulo arithmetic. The master system test file, test.S, found in the sw/zasm directory has been updated to reflect these new capabilities. (I really need to move it to the bench/asm directory, so you may expect that change sometime later.)	dgisselq	3363d 08h	/zipcpu/trunk/rtl/aux/busdelay.v
15	Updated the core CPUOPS module to make certain that the carry was properly set on right shifts. (Carry is then the last bit shifted out to the right, and has no relation to the high order bits of the word.) Also fixed a bug in the busdelay.v file that prevented our Quad SPI flash controller from working. (This bug fix has not yet been tested ...) Our test.S program, the closest thing we have to a regression test and found in the sw/zasm directory, still successfully passes in Verilator.	dgisselq	3376d 15h	/zipcpu/trunk/rtl/aux/busdelay.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3393d 05h	/zipcpu/trunk/rtl/aux/busdelay.v

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