URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Rev 18

Rev	Log message	Author	Age	Path
15	Updated the core CPUOPS module to make certain that the carry was properly set on right shifts. (Carry is then the last bit shifted out to the right, and has no relation to the high order bits of the word.) Also fixed a bug in the busdelay.v file that prevented our Quad SPI flash controller from working. (This bug fix has not yet been tested ...) Our test.S program, the closest thing we have to a regression test and found in the sw/zasm directory, still successfully passes in Verilator.	dgisselq	3396d 12h	/zipcpu/trunk/rtl/core/cpuops.v
12	Bunch of changes while trying to get a hello world program: 1. Right shifts by 32 or more now result in zero, or all of the top bit in the case of ASRs. 2. zdump now properly includes addresses with dumped lines. 3. zparser now properly handles immediate values via the .DAT instruction.	dgisselq	3411d 03h	/zipcpu/trunk/rtl/core/cpuops.v
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3412d 09h	/zipcpu/trunk/rtl/core/cpuops.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3413d 02h	/zipcpu/trunk/rtl/core/cpuops.v