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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Rev 42

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Rev	Log message	Author	Age	Path
25	Lots of changes, hopefully all for the better. The result works in a simulator, although it has yet to be tested yet in an FPGA--so it may still have Xilinx build errors. 1. The wires brought from the CPU to the Zip System for the debug command register were adjusted. They now include GIE and SLEEP, but no longer include the step or break enable bits as these were fairly useless anyway. 2. The user and master A-Stall counters were re-labeled as instruction count counters (which is what they are now anyway). This is for performance reasons so that, after the fact, you can measure how many instructions per clock you were actually able to achieve. 3. The CPU debug access port stall was adjusted so that the data port no longer stalls when the CPU isn't halted. This can be useful, for example, when trying to determine where th program counter is at without stalling the CPU. (You'll still need to read two registers, the supervisor and user program counters, and reading these registers still requires a write to the debug command port first, so this still requires 4 single operand wishbone bus cycles.) 4. Signed and unsigned 16-bit multiply capabilities were added to the ALU (cpuops.v) and support added in the Zip CPU master file as well. 5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user interrupt the supervisor can tell that it was a user interrupt versus a hardware interrupt. This bit is set any time the user disables the GIE bit, and cleared any time the supervisor sets the GIE bit. 6. A reserved position was created in the CC register for a floating point enable flag. This flag is permanently false, however, on the current implementation as it doesn't implement floating point. 7. Logic was added to handle the break instruction. This instruction has now been tested successfully in the simulator. If a break is issued, the CPU will either halt (if in supervisor mode, or if in user mode with the break enable bit set in the CC register), or the CPU will trip an interrupt for the supervisor to transfer execution to a user-level debugging task. 8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was adjusted to keep the pipeline from stalling in thesee conditions. This lew logic works for an 'A' operand, or equivalently for a 'B' operand with no immediate. In the cases of such logic, the operand is loaded directly from the output of the ALU into the input of the ALU skipping the operand read stage of the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear if it will break timing requirements or not. (Goal is 100 MHz clock.) As of this new change, the CPU can now execute 0.48 instructions per clock, versus the 0.44 it was getting before, across the test set. 9. Sleep logic was adjusted to prevent the user from switching to supervisor mode and putting the processor to (infinite) sleep at the same time. The justification was the fact that a user should not be able to halt the CPU when other processes that might want it might still exist. Other changes were made as well, but to other portions of the project. Those will be checked in shortly.	dgisselq	3410d 16h	/zipcpu/trunk/rtl/core/cpuops.v
15	Updated the core CPUOPS module to make certain that the carry was properly set on right shifts. (Carry is then the last bit shifted out to the right, and has no relation to the high order bits of the word.) Also fixed a bug in the busdelay.v file that prevented our Quad SPI flash controller from working. (This bug fix has not yet been tested ...) Our test.S program, the closest thing we have to a regression test and found in the sw/zasm directory, still successfully passes in Verilator.	dgisselq	3420d 05h	/zipcpu/trunk/rtl/core/cpuops.v
12	Bunch of changes while trying to get a hello world program: 1. Right shifts by 32 or more now result in zero, or all of the top bit in the case of ASRs. 2. zdump now properly includes addresses with dumped lines. 3. zparser now properly handles immediate values via the .DAT instruction.	dgisselq	3434d 21h	/zipcpu/trunk/rtl/core/cpuops.v
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3436d 02h	/zipcpu/trunk/rtl/core/cpuops.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3436d 20h	/zipcpu/trunk/rtl/core/cpuops.v

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