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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Rev 138

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Rev	Log message	Author	Age	Path
138	This updates the CPU multiply instruction into a set of three instructions. MPY is a 32x32-bit multiply instruction, returning the low 32-bit result, MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI returns the upper 32-bits assuming the result was signed.	dgisselq	3128d 02h	/zipcpu/trunk/rtl/core/idecode.v
130	Simplified the lock logic, and removed it when pipelining was not defined. This also means the file is now dependent upon cpudefs.v. In another change, brev was modified so as not to update the flags. This makes it useable with GCC as a potential move or load immediate instruction.	dgisselq	3142d 17h	/zipcpu/trunk/rtl/core/idecode.v
118	Fixes two bugs: 1) in the early branching code within the instruction decoder. This prevented the early branching from working when built with Xilinx's tools, while the code worked with Verilator. 2) The CPU was not working with the traditional cache and early branching disabled. These two bugs masked each other. The replacement code is simpler.	dgisselq	3161d 18h	/zipcpu/trunk/rtl/core/idecode.v
105	Fixed some nasty early branching bugs. Adjusted the Makefile to declare that cpudefs.h was automatically generated from cpudefs.v, and made sure that zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define. In addition, the test.S was updated to test long jumps, the early branching bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC, and LDI #x,PC.	dgisselq	3186d 02h	/zipcpu/trunk/rtl/core/idecode.v
90	Removed MOV x(PC),PC from the list of possible early branching instructions. ADD X,PC and LDI X,PC are now the only recognized early branching instructions. This was done to spare logic, although I don't think I spared more than a LUT or two.	dgisselq	3226d 19h	/zipcpu/trunk/rtl/core/idecode.v
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3257d 21h	/zipcpu/trunk/rtl/core/idecode.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3264d 01h	/zipcpu/trunk/rtl/core/idecode.v

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