URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Rev 98

Rev	Log message	Author	Age	Path
90	Removed MOV x(PC),PC from the list of possible early branching instructions. ADD X,PC and LDI X,PC are now the only recognized early branching instructions. This was done to spare logic, although I don't think I spared more than a LUT or two.	dgisselq	3223d 14h	/zipcpu/trunk/rtl/core/idecode.v
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3254d 16h	/zipcpu/trunk/rtl/core/idecode.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3260d 20h	/zipcpu/trunk/rtl/core/idecode.v