URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Rev 38

Rev	Log message	Author	Age	Path
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3357d 09h	/zipcpu/trunk/rtl/core/memops.v
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3412d 07h	/zipcpu/trunk/rtl/core/memops.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3413d 01h	/zipcpu/trunk/rtl/core/memops.v