URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Rev 117

Rev	Log message	Author	Age	Path
88	Eliminated some warnings. The div fixes were to simplify the logic, even though the result is less readable ...	dgisselq	3273d 16h	/zipcpu/trunk/rtl/core/pfcache.v
82	Found and (I hope) fixed a nasty bug that would send the prefetch into an endless loop whenever you jumped to an instruction at the last location in an unloaded cache line.	dgisselq	3275d 15h	/zipcpu/trunk/rtl/core/pfcache.v
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3280d 18h	/zipcpu/trunk/rtl/core/pfcache.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3286d 22h	/zipcpu/trunk/rtl/core/pfcache.v