URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Rev 25

Rev	Log message	Author	Age	Path
18	A couple of changes: Registers can now be changed via the debug interface. Also, in anticipation of being able to interrupt the break the processor, the CPU now exports an interrupt line to the external environment to tell when it has been halted. Thus, if it gets halted by a break instruction, the ZipSystem will interrupt whatever's in its environment so that the debugger can come and examine its state. Oh, and one other: because you can't examine the state of the CPU without halting it, I modified the debug control register to export the four useful flags: break-enable, interrupts enabled, and sleep (step comes for free in this implementation).	dgisselq	3370d 03h	/zipcpu/trunk/rtl/core/pipefetch.v
11	This version works on an FPGA!!! (Or at least the wdt.S program passes ...)	dgisselq	3388d 16h	/zipcpu/trunk/rtl/core/pipefetch.v
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3389d 13h	/zipcpu/trunk/rtl/core/pipefetch.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3390d 06h	/zipcpu/trunk/rtl/core/pipefetch.v