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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Rev 207

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201 RTL files for the 8-bit capable ZipCPU. dgisselq 2797d 20h /zipcpu/trunk/rtl/core/pipemem.v
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2923d 20h /zipcpu/trunk/rtl/core/pipemem.v
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)		 dgisselq 3065d 14h /zipcpu/trunk/rtl/core/pipemem.v
131 Fixed a variable use before declaration error. dgisselq 3119d 14h /zipcpu/trunk/rtl/core/pipemem.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3240d 22h /zipcpu/trunk/rtl/core/pipemem.v
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.		 dgisselq 3301d 23h /zipcpu/trunk/rtl/core/pipemem.v
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.		 dgisselq 3312d 01h /zipcpu/trunk/rtl/core/pipemem.v
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.		 dgisselq 3321d 17h /zipcpu/trunk/rtl/core/pipemem.v

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