URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Rev 117

Rev	Log message	Author	Age	Path
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3286d 23h	/zipcpu/trunk/rtl/core/prefetch.v
63	Simplified bus interactions, and added support for detecting illegal instructions (i.e. bus errors) in the pipefetch routine.	dgisselq	3347d 23h	/zipcpu/trunk/rtl/core/prefetch.v
48	Files added/updated to get Dhrystone benchmark to work. Several fixes to the CPU in the process, 'cause it wasn't working. Stall-less ALU ops now work better, to include grabbing the memory result as it comes out of the memory unit and placing it straight into either ALU or memory unit for the next instruction.	dgisselq	3367d 17h	/zipcpu/trunk/rtl/core/prefetch.v
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3380d 01h	/zipcpu/trunk/rtl/core/prefetch.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3435d 17h	/zipcpu/trunk/rtl/core/prefetch.v