| Rev |
Log message |
Author |
Age |
Path |
| 209 |
8b bytes, + formal verification throughout + dcache |
dgisselq |
2077d 23h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 205 |
Updating core to current/best version, to include dblfetch support and full CIS support |
dgisselq |
2798d 11h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 201 |
RTL files for the 8-bit capable ZipCPU. |
dgisselq |
2817d 08h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 193 |
These changes make it so the ALU multiplies pass a test-bench. |
dgisselq |
2943d 08h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 179 |
Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary. |
dgisselq |
2992d 06h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 160 |
Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.) |
dgisselq |
3085d 02h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 145 |
This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before. |
dgisselq |
3118d 00h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 132 |
Lots of minor bug fixes. |
dgisselq |
3139d 02h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 118 |
Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler. |
dgisselq |
3158d 03h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 105 |
Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC. |
dgisselq |
3182d 11h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 91 |
Minor updates. |
dgisselq |
3223d 04h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3249d 02h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 71 |
This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus. |
dgisselq |
3254d 06h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3260d 10h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 65 |
Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any. |
dgisselq |
3321d 10h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 56 |
Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.
A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used. |
dgisselq |
3331d 13h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 48 |
Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction. |
dgisselq |
3341d 04h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 38 |
A couple of quick updates:
- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.
Documentation changes coming shortly. |
dgisselq |
3344d 10h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3353d 13h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 34 |
Bunches of changes, although very little changed with the core itself.
Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.
There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.
Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.
Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.
The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.) |
dgisselq |
3379d 08h |
/zipcpu/trunk/rtl/core/zipcpu.v |
