| Rev |
Log message |
Author |
Age |
Path |
| 25 |
Lots of changes, hopefully all for the better. The result works in a
simulator, although it has yet to be tested yet in an FPGA--so it may still
have Xilinx build errors.
1. The wires brought from the CPU to the Zip System for the debug command
register were adjusted. They now include GIE and SLEEP, but no longer include
the step or break enable bits as these were fairly useless anyway.
2. The user and master A-Stall counters were re-labeled as instruction count
counters (which is what they are now anyway). This is for performance reasons
so that, after the fact, you can measure how many instructions per clock
you were actually able to achieve.
3. The CPU debug access port stall was adjusted so that the data port no longer
stalls when the CPU isn't halted. This can be useful, for example, when trying
to determine where th program counter is at without stalling the CPU. (You'll
still need to read two registers, the supervisor and user program counters, and
reading these registers still requires a write to the debug command port first,
so this still requires 4 single operand wishbone bus cycles.)
4. Signed and unsigned 16-bit multiply capabilities were added to the ALU
(cpuops.v) and support added in the Zip CPU master file as well.
5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user
interrupt the supervisor can tell that it was a user interrupt versus a hardware
interrupt. This bit is set any time the user disables the GIE bit, and cleared
any time the supervisor sets the GIE bit.
6. A reserved position was created in the CC register for a floating point
enable flag. This flag is permanently false, however, on the current
implementation as it doesn't implement floating point.
7. Logic was added to handle the break instruction. This instruction has now
been tested successfully in the simulator. If a break is issued, the CPU will
either halt (if in supervisor mode, or if in user mode with the break enable
bit set in the CC register), or the CPU will trip an interrupt for the
supervisor to transfer execution to a user-level debugging task.
8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was
adjusted to keep the pipeline from stalling in thesee conditions. This lew
logic works for an 'A' operand, or equivalently for a 'B' operand with no
immediate. In the cases of such logic, the operand is loaded directly from the
output of the ALU into the input of the ALU skipping the operand read stage of
the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear
if it will break timing requirements or not. (Goal is 100 MHz clock.) As
of this new change, the CPU can now execute 0.48 instructions per clock, versus
the 0.44 it was getting before, across the test set.
9. Sleep logic was adjusted to prevent the user from switching to supervisor
mode and putting the processor to (infinite) sleep at the same time. The
justification was the fact that a user should not be able to halt the CPU when
other processes that might want it might still exist.
Other changes were made as well, but to other portions of the project. Those
will be checked in shortly. |
dgisselq |
3386d 21h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 18 |
A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.
Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation). |
dgisselq |
3392d 21h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 9 |
This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.
Lots of work to get it working.
Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself. |
dgisselq |
3412d 00h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 3 |
Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.
Other tweaks were made to try to reduce code complexity. |
dgisselq |
3412d 08h |
/zipcpu/trunk/rtl/core/zipcpu.v |
| 2 |
An initial load. No promises of what works or not, but this is where the
project is at. |
dgisselq |
3413d 01h |
/zipcpu/trunk/rtl/core/zipcpu.v |
