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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 1917d 14h /zipcpu/trunk/rtl/peripherals/wbdmac.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2656d 23h /zipcpu/trunk/rtl/peripherals/wbdmac.v
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.		 dgisselq 2831d 21h /zipcpu/trunk/rtl/peripherals/wbdmac.v
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)		 dgisselq 2924d 16h /zipcpu/trunk/rtl/peripherals/wbdmac.v
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...		 dgisselq 3086d 18h /zipcpu/trunk/rtl/peripherals/wbdmac.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3100d 01h /zipcpu/trunk/rtl/peripherals/wbdmac.v
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.		 dgisselq 3180d 19h /zipcpu/trunk/rtl/peripherals/wbdmac.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3193d 04h /zipcpu/trunk/rtl/peripherals/wbdmac.v

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