URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Rev 209

Rev	Log message	Author	Age	Path
209	8b bytes, + formal verification throughout + dcache	dgisselq	2084d 05h	/zipcpu/trunk/rtl/peripherals/zipcounter.v
201	RTL files for the 8-bit capable ZipCPU.	dgisselq	2823d 14h	/zipcpu/trunk/rtl/peripherals/zipcounter.v
181	Adjusted the wishbone logic to include our wishbone simplification that if CYC is ever low, STB must be low as well.	dgisselq	2998d 12h	/zipcpu/trunk/rtl/peripherals/zipcounter.v
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	3091d 08h	/zipcpu/trunk/rtl/peripherals/zipcounter.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3266d 16h	/zipcpu/trunk/rtl/peripherals/zipcounter.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3415d 11h	/zipcpu/trunk/rtl/peripherals/zipcounter.v