URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipjiffies.v] - Rev 182

Rev	Log message	Author	Age	Path
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	3101d 12h	/zipcpu/trunk/rtl/peripherals/zipjiffies.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3276d 20h	/zipcpu/trunk/rtl/peripherals/zipjiffies.v
9	This checkin is the result of a watchdog timer test, and everything it took to get the watchdog timer working. The timer function was simplified, although it now uses a touch more resources--being able to count down 31 bits instead of 30. The parser was modified, since it couldn't handle storing to register plus offsets like it was supposed to be able to. The testbench, zippy_tb, was modified to accept an assembled machine code file such as I might place on a board to test it. Lots of work to get it working. Looking at the files below, it looks like I'll need a second check in to check in the watchdog timer test itself.	dgisselq	3424d 14h	/zipcpu/trunk/rtl/peripherals/zipjiffies.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3425d 15h	/zipcpu/trunk/rtl/peripherals/zipjiffies.v