OpenCores

URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [ziptimer.v] - Rev 66

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
56	Here's a bit of work in progress for getting the Zip CPU working on a XuLA2 board. Many changes include: the existence of a cpudefs.v file to control what "options" are included in the ZipCPU build. This allows build control to be separated from the project directory (one build for a XuLA2 board, another for a Basys-3 development board). Other changes have made things perhaps harder to read, but they get rid of warnings from XST. A big change was the addition of the (* ram_style="distributed" *) comment for the register set. This was necessary to keep XST from inferring a block RAM and breaking the logic that was supposed to take place between a register read and when it was used.	dgisselq	3312d 20h	/zipcpu/trunk/rtl/peripherals/ziptimer.v
9	This checkin is the result of a watchdog timer test, and everything it took to get the watchdog timer working. The timer function was simplified, although it now uses a touch more resources--being able to count down 31 bits instead of 30. The parser was modified, since it couldn't handle storing to register plus offsets like it was supposed to be able to. The testbench, zippy_tb, was modified to accept an assembled machine code file such as I might place on a board to test it. Lots of work to get it working. Looking at the files below, it looks like I'll need a second check in to check in the watchdog timer test itself.	dgisselq	3389d 11h	/zipcpu/trunk/rtl/peripherals/ziptimer.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3390d 12h	/zipcpu/trunk/rtl/peripherals/ziptimer.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.