URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Rev 12

Rev	Log message	Author	Age	Path
11	This version works on an FPGA!!! (Or at least the wdt.S program passes ...)	dgisselq	3414d 08h	/zipcpu/trunk/rtl/zipsystem.v
9	This checkin is the result of a watchdog timer test, and everything it took to get the watchdog timer working. The timer function was simplified, although it now uses a touch more resources--being able to count down 31 bits instead of 30. The parser was modified, since it couldn't handle storing to register plus offsets like it was supposed to be able to. The testbench, zippy_tb, was modified to accept an assembled machine code file such as I might place on a board to test it. Lots of work to get it working. Looking at the files below, it looks like I'll need a second check in to check in the watchdog timer test itself.	dgisselq	3414d 22h	/zipcpu/trunk/rtl/zipsystem.v
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3415d 06h	/zipcpu/trunk/rtl/zipsystem.v
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3415d 23h	/zipcpu/trunk/rtl/zipsystem.v