URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [zopcodes.h] - Rev 182

Rev	Log message	Author	Age	Path
89	Minor changes, to include making default branching an ADD.[condition] X,PC instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions. Further zopcodes.cpp contains several bug fixes.	dgisselq	3240d 10h	/zipcpu/trunk/sw/zasm/zopcodes.h
70	Updated the assembler support files, zopcodes in particular, to handle the disassembly of the new very long instruction word codes.	dgisselq	3271d 12h	/zipcpu/trunk/sw/zasm/zopcodes.h
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3277d 16h	/zipcpu/trunk/sw/zasm/zopcodes.h
13	Finally! The beginnings of the new assembler. It's not really polished yet, and it is quite clunky, but it works!! (Lots of bugs and features left to fix/implement: #include, #define macro(), #line tracking through the preprocessor, a means of finding include files (and the preprocessor!) and more. But, as a beginning, the basics are functinoal.	dgisselq	3409d 21h	/zipcpu/trunk/sw/zasm/zopcodes.h
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3426d 11h	/zipcpu/trunk/sw/zasm/zopcodes.h