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Rev Log message Author Age Path
118 Update components to be compatible with Terasic DE1 implementation dilbert57 4927d 23h /
117 Update Terasic DE1 implementation dilbert57 4928d 00h /
116 Update Terasic DE1 implementation dilbert57 4928d 00h /
115 Fold in Johns changes davidgb 4985d 14h /
114 Renamed project from my_sytem09 to system09 davidgb 4985d 14h /
113 clean cleans up more temp files davidgb 4985d 15h /
112 Branching at last known working XSA-3S1000 model. davidgb 4986d 01h /
111 Renamed project from my_system09 to system09 davidgb 4986d 01h /
110 Changes from John davidgb 4987d 13h /
109 Changes from John davidgb 4987d 13h /
108 Changes from John davidgb 4987d 13h /
107 Changes from John davidgb 4987d 13h /
106 davidgb 4992d 08h /
105 davidgb 4993d 02h /
104 davidgb 4993d 02h /
103 davidgb 4993d 02h /
102 davidgb 4993d 02h /
101 davidgb 4993d 02h /
100 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4993d 02h /
99 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4993d 02h /
98 renamed bram ports davidgb 4994d 02h /
97 renamed bram ports davidgb 4994d 02h /
96 renamed bram ports davidgb 4994d 02h /
95 renamed bram ports davidgb 4994d 02h /
94 renamed bram ports davidgb 4994d 02h /
93 Select b16 for BRAM_TYPE davidgb 4994d 05h /
92 Select b16 for BRAM_TYPE davidgb 4994d 05h /
91 Use BRAM_TYPE variable to select bram generation by s19tovhd davidgb 4994d 05h /
90 Modified to allow generation of two flavors of BRAMS:
b16 for Xilinx Spartan3
b4 for Xilinx Spartan2?
davidgb 4994d 05h /
89 whitespace davidgb 4995d 06h /

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