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[/] [System09/] - Rev 216

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Rev Log message Author Age Path
216 Get rid of warning about unconnected CLK0 pin davidgb 1087d 07h /System09/
215 Update project after switching to xilinx block ram davidgb 1087d 10h /System09/
214 Switch to Xilinx block ram davidgb 1087d 10h /System09/
213 updated project file davidgb 1087d 11h /System09/
212 Switched from VGA output to HDMI output. davidgb 1087d 11h /System09/
211 New version of VDU8 that has HDMI output. Still needs work refactoring clock signals. davidgb 1087d 11h /System09/
210 Check in code fragment implementing HDMI/TMDS encoding.
Derived from HDMI_test.v https://www.fpga4fun.com/HDMI.html (c) fpga4fun.com & KNJN LLC 2013
davidgb 1087d 11h /System09/
209 Started adding in keyboard (not tested).
Added in green-only VGA output thru Pmod port to PmodVGA J2 port.
Started working on HDMI output
davidgb 1087d 13h /System09/
208 swapped 32k and 16k ram to use block_spram. davidgb 1131d 14h /System09/
207 Updated design to pick up vdu8_spram (which uses parameterized ram for video memory instead of hard macros) davidgb 1131d 14h /System09/
206 Update comment/cleanup davidgb 1131d 14h /System09/
205 A new version of VDU8 that uses the parameterized xilinx ram "block_spram" for the video memory. davidgb 1131d 14h /System09/
204 patched up ram for zybo use davidgb 1131d 14h /System09/
203 Added a parameterized ram model. davidgb 1131d 14h /System09/
202 Updated Zybo design to reintroduce VDU8 driving the PmodVGA on pmod connectors JC+JD.
This version also uses PmodUSBUART on JE. To use PmodRS232 you must edit the .ucf file and select the appropriate pin LOCs.
davidgb 1131d 15h /System09/
201 A copy of XSA-3S1000.ucf and System09_Xess_XSA-3S1000.vhd that have dual serial ports with no handshake. davidgb 1138d 10h /System09/
200 Started adding back in video support - VDU8 instantiated and RGBHV bits sent to Pmod JE port. davidgb 1145d 07h /System09/
199 Add in full RS-232 handshake for PmodUSBUART. davidgb 1146d 09h /System09/
198 Update UCF file to select Pmod pinout compatible with the PmodUSBUART.
To use, make sure PmodUSBUART has JP1 as "LCL". Connect the usb to the uart and open the terminal program. Test the transmission via the LED on the Pmod. Then (carefully) plug into Pmod port on Zybo.
davidgb 1146d 10h /System09/
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 1153d 07h /System09/

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