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[/] [System09/] [trunk/] [rtl/] [VHDL/] - Rev 223

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Rev Log message Author Age Path
223 -- 0.3 David Burnette 8 April 2021 Added read-back of clk/transfer size
-- as well as a debug tag to confirm
-- read operation
davidgb 1107d 13h /System09/trunk/rtl/VHDL/
214 Switch to Xilinx block ram davidgb 1110d 20h /System09/trunk/rtl/VHDL/
211 New version of VDU8 that has HDMI output. Still needs work refactoring clock signals. davidgb 1110d 21h /System09/trunk/rtl/VHDL/
206 Update comment/cleanup davidgb 1155d 00h /System09/trunk/rtl/VHDL/
205 A new version of VDU8 that uses the parameterized xilinx ram "block_spram" for the video memory. davidgb 1155d 00h /System09/trunk/rtl/VHDL/
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 1176d 17h /System09/trunk/rtl/VHDL/
139 format davidgb 1466d 23h /System09/trunk/rtl/VHDL/
138 Remove DOS format davidgb 1466d 23h /System09/trunk/rtl/VHDL/
130 updated cpus & mul/div dilbert57 2169d 14h /System09/trunk/rtl/VHDL/
122 dilbert57 4577d 07h /System09/trunk/rtl/VHDL/
118 Update components to be compatible with Terasic DE1 implementation dilbert57 4907d 11h /System09/trunk/rtl/VHDL/
100 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4972d 14h /System09/trunk/rtl/VHDL/
99 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4972d 14h /System09/trunk/rtl/VHDL/
66 New directory structure. root 5520d 09h /System09/trunk/rtl/VHDL/
65 added new files davidgb 5527d 21h /System09/trunk/rtl/VHDL/
22 Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card. dilbert57 5881d 03h /System09/trunk/rtl/VHDL/
19 New directory structure dilbert57 5977d 03h /System09/trunk/rtl/VHDL/

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