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[/] [a-z80/] [trunk/] [cpu/] [top-level-files.txt] - Rev 19

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Rev	Log message	Author	Age	Path
19	Some documentation updates	gdevic	1981d 07h	/a-z80/trunk/cpu/top-level-files.txt
18	Correctly latch IO RW wait request Fixed bug: Issuing nWAIT during IO RW was ignored (IORQ, not M1) Taping into a correct point of IORQ generator sequence train gives an additional signal to be OR-ed when composing a generic latch_wait Corrected unconnected enable line	gdevic	2258d 21h	/a-z80/trunk/cpu/top-level-files.txt
17	z80: Release 5	gdevic	2666d 21h	/a-z80/trunk/cpu/top-level-files.txt
13	Full support for nWAIT during M1 and memory cycles This set of changes fixes issues with nWAIT signal Updated reg control, resets, ir modules to handle delay This correctly delays clearing of IR if the nWAIT was asserted at the very first M1 cycle Simplify decode_state to use discrete write enable for CB/ED flags Gate CB/ED write with hold_clk_wait to enable nWAIT delay genfuse add code to test nWAIT insertion at M1 Add host wait state circuitry from Zilog manual (wait_state.*) Add wait test code to basic fpga/modelsim models Select from 3 options to test wait states: - no wait state inserted (nWAIT=1) - insert a wait state to every M1 cycle - insert a wait state to each memory access cycle zxspectrum: Add custom NMI handler and a function to enter game pokes after pressing the NMI button zxspectrum: Corrected bits 7,5 when reading ULA port 254 zxspectrum: Fix the shift key repeat bug When using additional keys (<,>,?,...) and shift was released before a symbol, it would repeat. This change fixes that by correctly resetting keyboard mask state bitfields. Added new data pins module for Lattice toolset It has been reported that "data_pins.v" does not compile on Lattice toolset and this variation of the code has been proposed and verified by a user. Fixed M1 during reset Memory_ifc module set M1 to inactive (high) during nRESET Exported wait_m1 signal from that module as a testpoint	gdevic	2700d 21h	/a-z80/trunk/cpu/top-level-files.txt
8	z80: Release 4	gdevic	2972d 09h	/a-z80/trunk/cpu/top-level-files.txt
6	Added deployment folder with all files needed to use the CPU Changed ZX Spectrum project to use deployment files as example Changed extension for Verilog include files from .i to .vh Updated documentation; added section on file generators Minor corrections and fixes to various files	gdevic	3387d 00h	/a-z80/trunk/cpu/top-level-files.txt
3	- New directory structure - Added documentation files (and PDF versions) - Fixed tests	gdevic	3422d 14h	/a-z80/trunk/cpu/top-level-files.txt

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