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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_wb_if.v] - Rev 21

Rev	Log message	Author	Age	Path
20		root	5507d 20h	/ac97/trunk/rtl/verilog/ac97_wb_if.v
17	New directory structure.	root	5564d 00h	/ac97/trunk/rtl/verilog/ac97_wb_if.v
14	Fixed a bug reported by Igor. Apparently this bug only shows up when the WB clock is very low (2x bit_clk). Updated Copyright header.	rudi	7928d 05h	/ac97/trunk/rtl/verilog/ac97_wb_if.v
10	- Fixed the order of the thrash hold bits to match the spec. - Many minor synthesis cleanup items ...	rudi	8126d 07h	/ac97/trunk/rtl/verilog/ac97_wb_if.v
6	- Removed RTY_O output. - Added Clock and Reset Inputs to documentation. - Changed IO names to be more clear. - Uniquifyed define names to be core specific.	rudi	8333d 03h	/ac97/trunk/rtl/verilog/ac97_wb_if.v
4	- Changed to new directory structure	rudi	8340d 04h	/ac97/trunk/rtl/verilog/ac97_wb_if.v