URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Rev 69

Rev	Log message	Author	Age	Path
69	Removed #1 delays from tap core, changed DOS line breaks to UNIX.	nyawn	4485d 01h	/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v
32	Added a hi-speed mode via a change in protocol in the adv_dbg_if core. This should provide an order-of-magnitude speed improvement for some USB JTAG cables. Updated adv_jtag_bridge to match. Updated adv_dbg_if testbenches. Updated documents to reflect the new hi-speed mode. Added alternate USB-Blaster driver based on libftdi, donated by Xianfeng Zeng. Various bugfixes.	nyawn	5218d 03h	/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v
14	Added support for the legacy hardware debug unit (debug_if) to adv_jtag_bridge. Re-factored adv_jtag_bridge, removed many compilation warnings. Renamed some signals in the TAP cores for clarity. Updated documents.	nyawn	5433d 03h	/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v
8	Moved sub-modules to the correct subdirectories.	nyawn	5462d 03h	/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v
3	HDL cores which make up the hardware portion of the Advanced Debug System.	nyawn	5462d 03h	/adv_debug_sys/trunk/Hardware/jtag/tap/rtl/verilog/tap_top.v