URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [tags/] [AEMB_7_05/] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5549d 18h	/aemb/tags/AEMB_7_05/
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6212d 04h	/tags/AEMB_7_05/
36	Removed asynchronous reset signal.	sybreon	6212d 04h	/trunk/
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6213d 00h	/trunk/
34	Corrected speed issues after rev 1.9 update.	sybreon	6213d 14h	/trunk/
33	Fixed minor data hazard bug spotted by Matt Ettus.	sybreon	6228d 21h	/trunk/
32	Modified compilation sequence.	sybreon	6228d 21h	/trunk/
31	Removed byte acrobatics.	sybreon	6228d 21h	/trunk/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6231d 21h	/trunk/
29	Added code documentation. Added new tests that test floating point, modulo arithmetic and multiplication/division.	sybreon	6231d 21h	/trunk/
28	Fixed simulation bug.	sybreon	6231d 21h	/trunk/
27	Removed some unnecessary bubble control.	sybreon	6232d 08h	/trunk/
26	Fixed minor synthesis bug.	sybreon	6232d 08h	/trunk/
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6232d 12h	/trunk/
24	Made minor performance optimisations.	sybreon	6232d 22h	/trunk/
23	Fixed minor simulation bug.	sybreon	6233d 14h	/trunk/
22	Added support for 8-bit and 16-bit data types.	sybreon	6233d 14h	/trunk/
21	Added hierarchy block diagram.	sybreon	6243d 20h	/trunk/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6244d 10h	/trunk/
19	Added initial unified memory core.	sybreon	6246d 00h	/trunk/