URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [bench/] [tb_kat.v] - Rev 11

Rev	Log message	Author	Age	Path
11	Corrected a small problem with the KAT testbench.	motilito	4013d 10h	/aes_highthroughput_lowarea/trunk/verilog/bench/tb_kat.v
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4414d 09h	/aes_highthroughput_lowarea/trunk/verilog/bench/tb_kat.v
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	4869d 07h	/aes_highthroughput_lowarea/trunk/verilog/bench/tb_kat.v