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Rev Log message Author Age Path
32 Switch memory interfaces to Wishbone (pipelined).
Various bug fixes and improvements.		 ultra_embedded 3793d 05h /
31 Improvements to the execute stage logic. ultra_embedded 3813d 06h /
30 Fix verilog issues which break in XST. ultra_embedded 3897d 08h /
29 Added top level makefile ultra_embedded 3897d 11h /
28 Added instruction set simulator ultra_embedded 3897d 11h /
27 Initial drop of AltOR32 v2 ultra_embedded 3898d 05h /
26 Prepare for new release ultra_embedded 3898d 05h /
25 Added Papilio Pro (XC6LX9) project.

http://papilio.gadgetfactory.net/index.php?n=Papilio.PapilioPro		 ultra_embedded 4093d 07h /
24 Re-sync from local repository. ultra_embedded 4093d 08h /
23 - Bootloader code clean-up. ultra_embedded 4331d 08h /
22 - Added RTOS example project. ultra_embedded 4331d 09h /
21 - Added RTOS with port for AltOR32. ultra_embedded 4331d 10h /
20 - Added GPIO peripheral (with interrupt support). ultra_embedded 4331d 11h /
19 - IRQ_STATUS now reports all interrupts regardless of IRQ_MASK status. ultra_embedded 4331d 11h /
18 - Fixed sign extension handling of some l.sf**ui instructions. ultra_embedded 4336d 01h /
17 - Option to specify IRQ vector offset. ultra_embedded 4339d 02h /
16 - Clean-up. ultra_embedded 4339d 02h /
15 - Improved peripheral register interface.
- Papilio XC3S250E FPGA project now uses pipelined core @ 32MHz.		 ultra_embedded 4339d 09h /
14 Added initial version of pipelined AltOR32 core. ultra_embedded 4339d 12h /
13 Fixed l.lhs sign extension bug.
Removed duplicate instruction definitions.		 ultra_embedded 4345d 12h /
12 - Removed broken memory stall signal support on basic implementation. ultra_embedded 4359d 01h /
11 - Added missing library file. ultra_embedded 4360d 04h /
10 - Added example Papilio One (XC3S250E) project.
Contains bootloader accessible via USB uart @ 115200.		 ultra_embedded 4360d 05h /
9 - Added bin->Xilinx blockRAM init tool. ultra_embedded 4360d 05h /
8 - Added X-Modem bootloader ultra_embedded 4360d 05h /
7 - Fixed verilator makefile. ultra_embedded 4360d 05h /
6 - Simplified interrupt handling
- Added optional boot address argument		 ultra_embedded 4360d 05h /
5 Added verilator simulation.
Added basic peripherals & soc.		 ultra_embedded 4362d 00h /
4 Added initial basic core RTL implementation (non-pipelined). ultra_embedded 4362d 01h /
3 Added top level makefile.
Builds simulator & executes basic test image.		 ultra_embedded 4366d 06h /

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