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[/] [altor32/] - Rev 16

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Rev Log message Author Age Path
16 - Clean-up. ultra_embedded 4318d 13h /altor32/
15 - Improved peripheral register interface.
- Papilio XC3S250E FPGA project now uses pipelined core @ 32MHz.		 ultra_embedded 4318d 20h /altor32/
14 Added initial version of pipelined AltOR32 core. ultra_embedded 4319d 00h /altor32/
13 Fixed l.lhs sign extension bug.
Removed duplicate instruction definitions.		 ultra_embedded 4325d 00h /altor32/
12 - Removed broken memory stall signal support on basic implementation. ultra_embedded 4338d 13h /altor32/
11 - Added missing library file. ultra_embedded 4339d 16h /altor32/
10 - Added example Papilio One (XC3S250E) project.
Contains bootloader accessible via USB uart @ 115200.		 ultra_embedded 4339d 16h /altor32/
9 - Added bin->Xilinx blockRAM init tool. ultra_embedded 4339d 16h /altor32/
8 - Added X-Modem bootloader ultra_embedded 4339d 16h /altor32/
7 - Fixed verilator makefile. ultra_embedded 4339d 16h /altor32/
6 - Simplified interrupt handling
- Added optional boot address argument		 ultra_embedded 4339d 16h /altor32/
5 Added verilator simulation.
Added basic peripherals & soc.		 ultra_embedded 4341d 12h /altor32/
4 Added initial basic core RTL implementation (non-pipelined). ultra_embedded 4341d 12h /altor32/
3 Added top level makefile.
Builds simulator & executes basic test image.		 ultra_embedded 4345d 17h /altor32/
2 Added a simple simulator for OpenRisc 1000, where only the essential instructions have been implemented.

Runs code compiled with the following flags:
-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext		 ultra_embedded 4345d 18h /altor32/
1 The project and the structure was created root 4346d 15h /altor32/

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