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[/] [altor32/] - Rev 22

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Rev Log message Author Age Path
22 - Added RTOS example project. ultra_embedded 4307d 20h /altor32/
21 - Added RTOS with port for AltOR32. ultra_embedded 4307d 21h /altor32/
20 - Added GPIO peripheral (with interrupt support). ultra_embedded 4307d 22h /altor32/
19 - IRQ_STATUS now reports all interrupts regardless of IRQ_MASK status. ultra_embedded 4307d 22h /altor32/
18 - Fixed sign extension handling of some l.sf**ui instructions. ultra_embedded 4312d 12h /altor32/
17 - Option to specify IRQ vector offset. ultra_embedded 4315d 13h /altor32/
16 - Clean-up. ultra_embedded 4315d 13h /altor32/
15 - Improved peripheral register interface.
- Papilio XC3S250E FPGA project now uses pipelined core @ 32MHz.		 ultra_embedded 4315d 20h /altor32/
14 Added initial version of pipelined AltOR32 core. ultra_embedded 4315d 23h /altor32/
13 Fixed l.lhs sign extension bug.
Removed duplicate instruction definitions.		 ultra_embedded 4321d 23h /altor32/
12 - Removed broken memory stall signal support on basic implementation. ultra_embedded 4335d 12h /altor32/
11 - Added missing library file. ultra_embedded 4336d 15h /altor32/
10 - Added example Papilio One (XC3S250E) project.
Contains bootloader accessible via USB uart @ 115200.		 ultra_embedded 4336d 16h /altor32/
9 - Added bin->Xilinx blockRAM init tool. ultra_embedded 4336d 16h /altor32/
8 - Added X-Modem bootloader ultra_embedded 4336d 16h /altor32/
7 - Fixed verilator makefile. ultra_embedded 4336d 16h /altor32/
6 - Simplified interrupt handling
- Added optional boot address argument		 ultra_embedded 4336d 16h /altor32/
5 Added verilator simulation.
Added basic peripherals & soc.		 ultra_embedded 4338d 11h /altor32/
4 Added initial basic core RTL implementation (non-pipelined). ultra_embedded 4338d 12h /altor32/
3 Added top level makefile.
Builds simulator & executes basic test image.		 ultra_embedded 4342d 17h /altor32/

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